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cy7c006a 16 k 8 dual-port static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-06045 rev. *h revised december 20, 2013 16 k 8 dual-port static ram features true dual-ported memory cells which allow simultaneous access of the same memory location 16 k 8 organization (cy7c006a) 0.35-micron cmos for optimum speed/power high-speed access: 20 ns low operating power ? active: i cc = 180 ma (typical) ? standby: i sb3 = 0.05 ma (typical) fully asynchronous operation automatic power-down expandable data bus to 16 bits or more using master/slave chip select when using more than one device on-chip arbitration logic semaphores included to permit software handshaking between ports int flags for port-to-port communication pin select for master or slave commercial temperature range available in 68-pin plcc (cy7c006a), 64-pin tqfp (cy7c006a) pb-free packages available i/o control address decode a 0l ?a 13l ce l oe l r/w l busy l i/o control interrupt semaphore arbitration sem l int l m/s logic block diagram a 0l ?a 13l true dual-ported ram array a 0r ?a 13r ce r oe r r/w r busy r sem r int r address decode a 0r ?a 13r [1] [1] r/w l oe l i/o 0l ?i/o 7l ce l r/w r oe r i/o 0r ?i/o 7r ce r 14 8 14 8 14 14 note 1. busy is an output in master mode and an input in slave mode. cy7c007a16 k 8 dual-port static ram
cy7c006a document number: 38-06045 rev. *h page 2 of 22 contents pin configurations ........................................................... 3 selection guide ................................................................ 4 pin definitions .................................................................. 4 architecture ...................................................................... 4 functional description ..................................................... 4 write operation ........................................................... 4 read operation ........................................................... 5 interrupts ..................................................................... 5 busy ............................................................................ 5 master/slave ............................................................... 5 semaphore operation ............ .............. .............. ......... 5 maximum ratings ............................................................. 6 operating range ............................................................... 6 electrical characteristics ................................................. 6 capacitance ...................................................................... 7 ac test loads and waveforms ....................................... 7 data retention mode ........................................................ 7 timing ................................................................................ 7 switching characteristics ................................................ 8 switching waveforms .................................................... 10 non-contending read/write .......................................... 16 interrupt operation example ......................................... 16 semaphore operation example .................................... 16 ordering information ...................................................... 17 16 k 8 asynchronous dual-port sram ................. 17 ordering code definitions ..... .................................... 17 package diagrams .......................................................... 18 acronyms ........................................................................ 20 document conventions ................................................. 20 units of measure ....................................................... 20 document history page ................................................. 21 sales, solutions, and legal information ...................... 22 worldwide sales and design s upport ......... .............. 22 products .................................................................... 22 psoc? solutions ...................................................... 22 cypress developer community ................................. 22 technical support ................. .................................... 22
cy7c006a document number: 38-06045 rev. *h page 3 of 22 pin configurations figure 1. 68-pin plcc pinout top view figure 2. 64-pin tqfp pinout top view v cc oe l i/o 1l i/o 0l a 12l a 11l a 10l a 9l a 8l a 7l a 6l a 13l ce l sem l r/w l i/o 2l i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l v cc gnd i/o 0r i/o 1r i/o 2r i/o 3r i/o 4r i/o 5r gnd v cc a 4l a 3l a 2l a 1l a 0l gnd busy l busy r m/s a 0r a 1r a 2r a 3r a 4r int l int r gnd oe r i/o 7r a 5r a 12r a 11r a 10r a 9r a 8r a 7r a 6r a 13r ce r sem r r/w r a 5l nc i/o6 r 24 25 26 10 11 12 13 14 15 48 47 46 45 44 40 41 27 42 28 43 29 30 31 32 33 68 34 67 35 66 36 65 37 64 38 63 39 62 61 16 59 58 57 56 55 54 53 52 51 50 49 60 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 nc nc nc cy7c006a (16 k 8) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 50 32 49 16 gnd oe r i/o 2l i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l v cc gnd i/o 0r i/o 1r i/o 2r i/o 3r i/o 4r i/o 5r i/o 6r gnd v cc a 4l a 3l a 2l a 1l a 0l gnd busy l busy r m/s a 0r a 1r a 2r a 3r a 4r int l int r i/o 7r a 5r a 12r a 11r a 10r a 9r a 8r a 7r a 6r a 13r ce r sem r r/w r v cc oe l i/o 1l i/o 0l a 5l a 12l a 11l a 10l a 9l a 8l a 7l a 6l a 13l ce l sem l r/w l cy7c006a (16 k 8)
cy7c006a document number: 38-06045 rev. *h page 4 of 22 architecture the cy7c006a consists of an array 16k words of 8 bits of dual-port ram cells, i/o and address lines, and control signals (ce , oe , r/w ). these control pins permit independent access for reads or writes to any location in memory. to handle simultaneous writes/reads to the same location, a busy pin is provided on each port. two interrupt (int ) pins can be utilized for port-to-port communication. two semaphore (sem ) control pins are used for allocating shared resources. with the m/s pin, the devices can function as a master (busy pins are outputs) or as a slave (busy pins are inputs). the devices also have an automatic power-down feature controlled by ce . each port is provided with its own output enable control (oe ), which allows data to be read from the device. functional description the cy7c006a is low-power cmos 16 k 8 dual-port static rams. various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. the devices can be utilized as standalone 8-bit dual-port static rams or multiple devices can be combined in order to function as a 16-bit or wider master/slave dual-port static ram. an m/s pin is provided for implementing 16-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. application areas include interprocessor/multipro cessor designs, communications status buffering, and dual-port video/graphics memory. each port has independent control pins: chip enable (ce ), read or write enable (r/w ), and output enable (oe ). two flags are provided on each port (busy and int ). busy signals that the port is trying to access the same location currently being accessed by the other port. the interrupt flag (int ) permits communication between ports or systems by means of a mail box. the semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphore logic is comprised of eight shared latches. only one side can control the latch (semaphor e) at any time. control of a semaphore indicates that a shared resource is in use. an automatic power-down feature is controlled independently on each port by a chip select (ce ) pin. the cy7c006a is available in 68-pin plcc package, the cy7c006a is also available in 64-pin tqfp package. write operation data must be set up for a duration of t sd before the rising edge of r/w in order to guarantee a valid write. a write operation is controlled by either the r/w pin (see write cycle no. 1 waveform) or the ce pin (see write cycle no. 2 waveform). required inputs for non-contention operations are summarized selection guide description cy7c006a -20 unit maximum access time 20 ns typical operating current 180 ma typical standby current for i sb1 (both ports ttl level) 45 ma typical standby current for i sb3 (both ports cmos level) 0.05 ma pin definitions left port right port description ce l ce r chip enable r/w l r/w r read/write enable oe l oe r output enable a 0l ?a 13l a 0r ?a 13r address i/o 0l ?i/o 7l i/o 0r ?i/o 7r data bus input/output sem l sem r semaphore enable int l int r interrupt flag busy l busy r busy flag m/s master or slave select v cc power gnd ground nc no connect
cy7c006a document number: 38-06045 rev. *h page 5 of 22 in non-contending read/write on page 16 . if a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is r ead on the output; otherwise the data read is not deterministic. data will be valid on the port t ddd after the data is presented on the other port. read operation when reading the device, the user must assert both the oe and ce pins. data will be available t ace after ce or t doe after oe is asserted. if the user wishes to access a semaphore flag, then the sem pin must be asserted instead of the ce pin, and oe must also be asserted. interrupts the upper two memory locations may be used for message passing. the highest memory location (3fff) is the mailbox for the right port and the second-highest memory location (3ffe) is the mailbox for the left port. w hen one port writes to the other port?s mailbox, an interrupt is generated to the owner. the interrupt is reset when the owner reads the contents of the mailbox. the message is user defined. each port can read the other po rt?s mailbox without resetting the interrupt. the active state of th e busy signal (to a port) prevents the port from setting the interrupt to the winning port. also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. if an application does not require message passing, do not connect the interrupt pin to the processor?s interrupt request input pin. the operation of the interrupts and their interaction with busy are summarized in interrupt operation example on page 16 . busy the cy7c006a provides on-chip arbitration to resolve simultaneous memory location access (contention). if both ports? ce s are asserted and an address match occurs within t ps of each other, the busy logic will determine which port has access. if t ps is violated, one port will definitely gain permission to the location, but it is not pred ictable which port will get that permission. busy will be asserted t bla after an address match or t blc after ce is taken low. master/slave a m/s pin is provided in order to expand the word width by configuring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. this will allow the device to interface to a master device with no external components. writing to slave devices must be delayed until after the busy input has settled (t blc or t bla ), otherwise, the slave chip may begin a write cycle during a contention situation. when tied high, the m/s pin allows the device to be used as a master and, therefore, the busy line is an output. busy can then be used to send the arbitration outcome to a slave. semaphore operation the cy7c006a provides eight se maphore latches, which are separate from the dual-port memory locations. semaphores are used to reserve resources that are shared between the two ports. the state of the semaphore indicates that a resource is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. the left port then verifies its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for t sop before attempting to read the semaphore. the semaphore value will be available t swrd + t doe after the rising edge of the semaphore write. if the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assume s the right port has control and continues to poll the semaphore. when the right side has relinquished control of the sema phore (by writing a one), the left side will succeed in gaining control of the semaphore. if the left side no longer requires the semaph ore, a one is written to cancel its request. semaphores are accessed by asserting sem low. the sem pin functions as a chip select for the semaphore latches (ce must remain high during sem low). a 0?2 represents the semaphore address. oe and r/w are used in the same manner as a normal memory access. when writing or reading a semaphore, the other addre ss pins have no effect. when writing to the semaphore, only i/o 0 is used. if a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. that semaphore can now only be modified by the side showing zero (the left port in this case). if the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. however, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. semaphore operation example on page 16 shows sample semaphore operations. when reading a semaphore, all data lines output the semaphore value. the read value is latched in an output register to prevent the semaphore from changing stat e during a write from the other port. if both ports attempt to access the semaphore within t sps of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
cy7c006a document number: 38-06045 rev. *h page 6 of 22 maximum ratings exceeding maximum ratings [2] may shorten the useful life of the device. user guidelines are not tested. storage temperature ................ ............... ?65 c to +150 c ambient temperature with power applied ........... ............... ............... ?55 c to +125 c supply voltage to ground potential .............?0.3 v to +7.0 v dc voltage applied to outputs in high z state .............................................?0.5 v to +7.0 v dc input voltage [3] .....................................?0.5 v to +7.0 v output current into outputs (low) ............................ 20 ma static discharge voltage ...... ........... ............ ............. > 2001v latch-up current ................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 5 v ? 10% electrical characteristics over the operating range parameter description cy7c006a unit -20 min typ max v oh output high voltage (v cc = min, i oh = ?4.0 ma) 2.4 ? ? v v ol output low voltage (v cc = min, i oh = +4.0 ma) ? 0.4 v v ih input high voltage 2.2 ? v v il input low voltage ? 0.8 v i oz output leakage current ?10 10 ? a i cc operating current (v cc = max, i out = 0 ma), outputs disabled commercial ? 180 275 ma industrial ? ma i sb1 standby current (both ports ttl level), ce l & ce r ? v ih , f = f max commercial 45 65 ma industrial ? ma i sb2 standby current (one port ttl level), ce l | ce r ? v ih , f = f max commercial 110 160 ma industrial ? ma i sb3 standby current (both ports cmos level), ce l & ce r ? v cc ?? 0.2 v, f = 0 commercial 0.05 0.5 ma industrial ? ma i sb4 standby current (one port cmos level), ce l | ce r ? v ih , f = f max [3, 4] commercial 100 140 ma industrial ? ma notes 2. the voltage on any input or i/o pin can not exceed the power pin during power-up. 3. pulse width < 20 ns. 4. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3 .
cy7c006a document number: 38-06045 rev. *h page 7 of 22 data retention mode the cy7c006a is designed with battery backup in mind. data retention voltage and supply current are guaranteed over temperature. the following rules ensure data retention: 1. chip enable (ce ) must be held high during data retention, within v cc to v cc ? 0.2 v. 2. ce must be kept between v cc ? 0.2 v and 70% of v cc during the power-up and power-down transitions. 3. the ram can begin operation >t rc after v cc reaches the minimum operating voltage (4.5 v). capacitance parameter [5] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0 v 10 pf c out output capacitance 10 pf ac test loads and waveforms figure 3. ac test loads and waveforms (a) normal load (load 1) r1 = 893 ? 5 v output r2 = 347 ? c= 30 pf v th = 1.4 v output c= 30 pf (b) thvenin equivalent (load 1) (c) three-state delay (load 2) r1 = 893 ? r2 = 347 ? 5 v output c= 5pf r th = 250 ? (used for t lz , t hz , t hzwe , & t lzwe including scope and jig) timing parameter test conditions [6] max unit icc dr1 @ vcc dr = 2 v 1.5 ma data retention mode 4.5v 4.5v v cc ? ? 2.0v v cc to v cc ? 0.2v v cc ce t rc v ih notes 5. tested initially and after any design or proc ess changes that may affect these parameters. 6. ce = v cc , v in = gnd to v cc , t a = 25c. this parameter is guaranteed but not tested.
cy7c006a document number: 38-06045 rev. *h page 8 of 22 switching characteristics over the operating range parameter [7] description cy7c006a unit -20 min max read cycle t rc read cycle time 20 ? ns t aa address to data valid ? 20 ns t oha output hold from address change 3 ? ns t ace [8] ce low to data valid ? 20 ns t doe oe low to data valid ? 12 ns t lzoe [9, 10, 11] oe low to low z 3 ? ns t hzoe [9, 10, 11] oe high to high z ? 12 ns t lzce [9, 10, 11] ce low to low z 3 ? ns t hzce [9, 10, 11] ce high to high z ? 12 ns t pu [11] ce low to power-up 0 ? ns t pd [11] ce high to power-down ? 20 ns write cycle t wc write cycle time 20 ? ns t sce [8] ce low to write end 15 ? ns t aw address valid to write end 15 ? ns t ha address hold from write end 0 ? ns t sa [8] address set-up to write start 0 ? ns t pwe write pulse width 15 ? ns t sd data set-up to write end 15 ? ns t hd [12] data hold from write end 0 ? ns t hzwe [10, 11] r/w low to high z ? 12 ns t lzwe [10, 11] r/w high to low z 3 ? ns t wdd [13] write pulse to data delay ? 45 ns t ddd [13] write data valid to read data valid ? 30 ns notes 7. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i oi /i oh and 30-pf load capacitance. 8. to access ram, ce = l, sem = h. to access semaphore, ce = h and sem = l. either condition must be valid for the entire t sce time. 9. at any given temperature and voltage condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 10. test conditions used are load 3. 11. this parameter is guaranteed but not tested. 12. for 15 ns industrial parts t hd min. is 0.5 ns. 13. for information on port-to-port delay through ram cells from writing port to reading port, refer to read timing with busy wa veform.
cy7c006a document number: 38-06045 rev. *h page 9 of 22 busy timing [14] t bla busy low from address match ? 20 ns t bha busy high from address mismatch ? 20 ns t blc busy low from ce low ? 20 ns t bhc busy high from ce high ? 17 ns t ps port set-up for priority 5 ? ns t wb r/w high after busy (slave) 0 ? ns t wh r/w high after busy high (slave) 15 ? ns t bdd [15] busy high to data valid ? 20 ns interrupt timing [14] t ins int set time ?20ns t inr int reset time ? 20 ns semaphore timing t sop sem flag update pulse (oe or sem )10?ns t swrd sem flag write to read time 5 ? ns t sps sem flag contention window 5 ? ns t saa sem address access time ? 20 ns switching characteristics (continued) over the operating range parameter [7] description cy7c006a unit -20 min max notes 14. test conditions used are load 2. 15. t bdd is a calculated parameter and is the greater of t wdd ?t pwe (actual) or t ddd ?t sd (actual).
cy7c006a document number: 38-06045 rev. *h page 10 of 22 switching waveforms figure 4. read cycle no. 1 (either port address access) [16, 17, 18] figure 5. read cycle no. 2 (either port ce /oe access) [16, 19, 20] figure 6. read cycle no. 3 (either port) [16, 18, 19, 20] t rc t aa t oha data valid previous data valid data out address t oha t ace t lzoe t doe t hzoe t hzce data valid t lzce t pu t pd i sb i cc data out oe ce current data out t rc address t aa t oha ce t lzce t abe t hzce t ace t lzce notes 16. r/w is high for read cycles. 17. device is continuously selected ce = v il . this waveform cannot be used for semaphore reads. 18. oe = v il . 19. address valid prior to or coincident with ce transition low. 20. to access ram, ce = v il , sem = v ih . to access semaphore, ce = v ih , sem = v il .
cy7c006a document number: 38-06045 rev. *h page 11 of 22 figure 7. write cycle no. 1: r/w controlled timing [21, 22, 23, 24] figure 8. write cycle no. 2: ce controlled timing [21, 22, 23, 28] switching waveforms (continued) t aw t wc t pwe t hd t sd t ha ce r/w oe data out data in address t hzoe t sa t hzwe t lzwe [26] [26] [24] [25] note 27 note 27 t aw t wc t sce t hd t sd t ha ce r/w data in address t sa [25] notes 21. r/w or ce must be high during all address transitions. 22. a write occurs during the overlap (t sce or t pwe ) of a low ce or sem . 23. t ha is measured from the earlier of ce or r/w or (sem or r/w ) going high at the end of write cycle. 24. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during an r/w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t pwe . 25. to access ram, ce = v il , sem = v ih . 26. transition is measured 500 mv from steady state with a 5-pf load (including scope and jig). this parameter is sampled and n ot 100% tested. 27. during this period, the i/o pins are in the output state, and input signals must not be applied. 28. if the ce or sem low transition occurs simult aneously with or after the r/w low transition, the outputs remain in the high-impedance state.
cy7c006a document number: 38-06045 rev. *h page 12 of 22 figure 9. semaphore read af ter write timing, either side [29] figure 10. timing diagram of semaphore contention [30, 31, 32] switching waveforms (continued) t sop t aa valid adress valid adress t hd data in valid data out valid t oha t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle oe r/w i/o 0 sem a 0 ?a 2 match t sps a 0l ?a 2l match r/w l sem l a 0r ?a 2r r/w r sem r notes 29. ce = high for the duration of the abov e timing (both writ e and read cycle). 30. i/o 0r = i/o 0l = low (request semaphore); ce r = ce l = high. 31. semaphores are reset (available to both ports) at cycle start. 32. if t sps is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpr edictable.
cy7c006a document number: 38-06045 rev. *h page 13 of 22 figure 11. timing diagram of read with busy (m/s = high) [33] figure 12. write timing with busy input (m/s = low) switching waveforms (continued) valid t ddd t wdd match match r/w r data in r data outl t wc address r t pwe valid t sd t hd address l t ps t bla t bha t bdd busy l t pwe r/w busy t wb t wh note 33. ce l = ce r = low.
cy7c006a document number: 38-06045 rev. *h page 14 of 22 figure 13. busy timing diagram no. 1 (ce arbitration) [34] figure 14. busy timing diagram no. 2 (address arbitration) [34] switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc ce r valid first: address l,r busy r ce l ce r busy l ce r ce l address l,r ce l valid first: address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r right address valid first: left address valid first: note 34. if t ps is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side busy will be asserted.
cy7c006a document number: 38-06045 rev. *h page 15 of 22 figure 15. interr upt timing diagrams switching waveforms (continued) write 3fff t wc t ha read 3fff t rc t inr write 3ffe t wc read 3ffe t inr t rc address r ce l r/w l int l oe l address r r/w r ce r int l address r ce r r/w r int r oe r address l r/w l ce l int r t ins t ha t ins [35] [36] [36] [36] [35] [36] left side sets int r : right side clears int r : right side sets int l : left side clears int l : notes 35. t ha depends on which enable pin (ce l or r/w l ) is deasserted first. 36. t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last.
cy7c006a document number: 38-06045 rev. *h page 16 of 22 non-contending read/write inputs outputs ce r/w oe sem i/o 0 ? i/o 8 operation h x x h high z deselected: power-down h h l l data out read data in semaphore flag x x h x high z i/o lines disabled h x l data in write into semaphore flag l h l h data out read l l x h data in write l x x l not allowed interrupt operation example (assumes busy l = busy r = high) left port right port function r/w l ce l oe l a 0 l ?14 l int l r/w r ce r oe r a 0r?14r int r set right int r flag l lx 3fff xxxx x l [37] reset right int r flag x x x x x x l l 3fff h [38] set left int l flag xxx x l [38] llx 3ffe x reset left int l flag x l l 3ffe h [37] xxxxx semaphore operation example function i/o 0 ? i/o 8 left i/o 0 ? i/o 8 right status no action 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token right port writes 0 to semaphore 0 1 no change. right side has no write access to semaphore left port writes 1 to semaphore 1 0 right port obtains semaphore token left port writes 0 to semaphore 1 0 no change. left port has no write access to semaphore right port writes 1 to semaphore 0 1 left port obtains semaphore token left port writes 1 to semaphore 1 1 semaphore free right port writes 0 to semaphore 1 0 right port has semaphore token right port writes 1 to semaphore 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token left port writes 1 to semaphore 1 1 semaphore free notes 37. if busy l = l, then no change. 38. if busy r = l, then no change.
cy7c006a document number: 38-06045 rev. *h page 17 of 22 ordering information ordering code definitions 16 k 8 asynchronous dual-port sram speed (ns) ordering code package name package type operating range 20 cy7c006a-20axc a65 64-pin tqfp (pb-free) commercial CY7C006A-20AXI a65 64-pin tqfp (pb-free) industrial cy7c006a-20jxc j81 68-pin plcc (pb-free) commercial temperature range: x = c or i c = commercial; i = industrial x = pb-free (rohs compliant) package type: x = a or j a = 64-pin tqfp j = 68-pin plcc speed grade: 20 ns 06a = depth: 16k 0 = width: 8 technology code: c = cmos marketing code: 7 = dual port sram company id: cy = cypress c cy 0 06a - 20 x x x 7
cy7c006a document number: 38-06045 rev. *h page 18 of 22 package diagrams figure 16. 64-pin tqfp (14 14 1. 4 mm) a64sa package outline, 51-85046 51-85046 *e
cy7c006a document number: 38-06045 rev. *h page 19 of 22 figure 17. 68-pin plcc (0.958 0. 958 inches) package outline, 51-85005 package diagrams (continued) 51-85005 *c
cy7c006a document number: 38-06045 rev. *h page 20 of 22 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output int interrupt oe output enable plcc plastic leaded chip carrier r/w read/write sram static random access memory tqfp thin quad flat pack ttl transistor-transistor logic symbol unit of measure c degree celsius a microampere ma milliampere ns nanosecond ? ohm % percent pf picofarad vvolt wwatt
cy7c006a document number: 38-06045 rev. *h page 21 of 22 document history page document title: cy7c006a, 16 k 8 dual-port static ram document number: 38-06045 rev. ecn no. issue date orig. of change description of change ** 110197 09/29/01 szv change from spec number: 38-00831 to 38-06045 *a 122295 12/27/02 rbi power up requirements added to maximum ratings information *b 237620 see ecn ydt removed cross information from features section *c 345376 see ecn aeq removed i-temp versions for both packages, since they are not valid part numbers. *d 387333 see ecn pcx included pb-free logo included package: cy7c006a-20ai included pb-free packages: cy7c006a-15axc, cy7c006a-20axc, CY7C006A-20AXI, cy7c006a-20jxc, cy7c007a-20jxc, cy7c016a-15axc *e 2896210 03/22/2010 rame updated ordering information updated package diagram *f 3110296 12/14/2010 eyb updated ordering information . added ordering code definitions . minor edits and updated in new template. *g 3889996 01/30/2013 smch removed cy7c007a, cy7c016a, cy7c017a related information across the document. updated package diagrams : spec 51-85046 ? changed revision from *d to *e. removed spec 51-85065 (corresponding to 80-pin tqfp package). spec 51-85005 ? changed revision from *b to *c. added acronyms and units of measure . *h 4227411 12/20/2013 smch updated ordering information (updated part numbers). updated in new template. completing sunset review.
document number: 38-06045 rev. *h revised december 20, 2013 page 22 of 22 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c006a ? cypress semiconductor corporation, 2001-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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